Taking up the 50Days verilog coding challenge. Contribute to Muttu96/Verilog-Challenge development by creating an account on GitHub.
In this repository, the implementation of an eBCH(256,239,2) product code encoder and a decoder on an RFSoC4x2 FPGA board is presented. The implementation is optimized to get a low BER rate of 10-14, ...
For my Senior Design project I am working with four others on a FPGA implementation of the ITU G.729 Encoder. We are writing the encoder in verilog code and building it onto a Xilinx Virtex-5 board.
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