Hackaday

MIPI CSI-2 Implementation In FPGAs

[Adam Taylor] always has interesting FPGA posts and his latest is no exception. He wanted to use a Zynq for image processing. Makes sense. You can do the high-speed parallel parts in the FPGA fabric ...
Design-Reuse

MIPI in FPGAs for mobile-influenced devices

A new wave of applications for mobile-influenced devices, using technology initially designed for mobile devices, demand high-resolution, high-frame-rate streaming data from vision sensors, especially ...
Business Wire

Mixel MIPI C-PHY/D-PHY Combo IP Integrated into Hercules Microelectronics HME-H3 FPGA

Mixel’s MIPI PHY IP integrated into the HME-H3 FPGA, the industry’s first FPGA to support MIPI C-PHY v2.0 SAN JOSE, Calif.--(BUSINESS WIRE)--Mixel ®, Inc. (Mixel), a leading provider of mixed-signal ...
GitHub

briansune/FPGA-TFT-MIPI-or-DPI

Xilinx - 7 series (Currently tested on Kintex 7 & Artix 7) Xilinx - 6 series (Currently tested on Spartan 6) Xilinx - Ultrascale+ / Ultrascale (Currently tested on ZYNQMP) Altera - Cyclone IV ...
Electronic Design

FPGA Bridges MIPI and More

Lattice Semiconductor’s CrossLinkPlus is designed to handle interface conversion, including support for MIPI virtual channels (Fig. 1). The chip will be useful to bridge between a peripheral’s ...
GitHub

briansune/FPGA-LCD-MIPI-or-DPI

Xilinx - 7 series (Currently tested on Kintex 7 & Artix 7) Xilinx - 6 series (Currently tested on Spartan 6) Xilinx - Ultrascale+ / Ultrascale (Currently tested on ZYNQMP) Altera - Cyclone IV ...
New Electronics

Arasan announces MIPI DSI IP for FPGA

Arasan has released a new version of its MIPI DSI IP that's compliant with the DSI-2 v1.0 Specifications supporting C-PHY v2.0 speeds of up to 54.72Gbps operating at 8 Gbps (for 1channel) for FPGA ...
Hackaday

Xilinx Makes MIPI CSI And DSI Controller IP Blocks Free To Use With Vivado

If you want to use a display or camera with an FPGA, you will often end up with a MIPI-based solution. As of the Xilinx Vivado 2020.1 release, the MIPI DSI (display serial interface) and CSI (camera ...
Design-Reuse

Arasan announces MIPI DSI IP for FPGA supporting full C-PHY 2.0 speeds

Arasan announces the immediate availability of its MIPI DSI IP supporting C-PHY v2.0 speeds of up to 54.72Gbps for FPGA designs November 8, 2022, San Jose, CA -- Arasan has released an all new version ...
Business Wire

MIPIアライアンスが車載向けA-PHY SerDesインターフェースをリリース

米ニュージャージー州ピスカタウェイ--(BUSINESS WIRE)--（ビジネスワイヤ） -- （ビジネスワイヤ） -- モバイル産業／モバイル関連産業向けのインターフェース仕様を策定する国際組織のMIPIアライアンスは本日、MIPI A-PHY v1.0の提供を開始したと発表しました。
CNX Software

Topaz Tz170b FPGA devkit features hardened LPDDR4 controller, hardened MIPI D-PHY up to 2 ...

The Topaz Tz170b FPGA devkit from Efinix is a compact FPGA evaluation platform built around the Efinix Tz170 FPGA. This FPGA is built around a low-power, high-density 16 nm Quantum fabric and comes in ...
EDN

MIPI C-PHY/D-PHY combo IP supports latest camera specs

A test chip incorporating Mixel’s MIPI C-PHY/D-PHY combo IP has been manufactured on STMicroelectronics’ 40-nm low-power process technology and it has been a first-time silicon success. Other MIPI IP ...