Business Wire

SiSoft and MathWorks to Demonstrate New Signal Integrity, SerDes, and Mixed-Signal Design ...

SANTA CLARA, Calif.--(BUSINESS WIRE)--SiSoft today announced new Signal Integrity, SerDes, and Mixed-Signal design solutions developed jointly with MathWorks which will be on display this week at ...
PR TIMES

スマートコックピットの普及に貢献！SoC向けPMICやSerDes IC等を搭載し ...

ローム株式会社（本社：京都市）は、スマートコックピット向けSoC(*1)メーカーの中国最大手、Nanjing SemiDrive Technology Ltd.（以下、SemiDrive）とスマートコックピット向けリファレンスデザイン「REF66004」を共同開発しました。このリファレンスデザインは ...
Semiconductor Engineering

Re-Architecting SerDes

Serializer/Deserializer (SerDes) circuits have been helping semiconductors move data around for years, but new process technologies are forcing it to adapt and change in unexpected ways. Traditionally ...
Semiconductor Engineering

The Challenges Of Designing 28G And 56G SerDes IP

The industry move to 56 Gbps PAM4 is undoubtedly one of the greatest challenges currently facing SerDes IP designers and their customers. To begin with, shifting to 56 Gbps PAM4 immediately causes a ...
Business Wire

Cadence Accelerates Hyperscale SoC Design with Next-Generation 112G Extended Long-Reach ...

SAN JOSE, Calif.--(BUSINESS WIRE)--Cadence Design Systems, Inc. (Nasdaq: CDNS) today unveiled its 112G Extended Long-Reach (112G-ELR) SerDes IP on TSMC’s N4P process for hyperscale ASICs, artificial ...
Design-Reuse

Multi-Gigabit SerDes: The Cornerstone of High Speed Serial Interconnects

As the CPU speed reaches 3GHz and beyond, the I/O performance of a PC has increasingly become the bottleneck of the overall system performance. Traditionally, the I/O- subsystems are connected to the ...
Design-Reuse

Cadence Expands Design IP Portfolio with 56G Long-Reach PAM4 SerDes on TSMC N7 and N6 Processes

DSP-based, multi-rate SerDes IP is optimized for power, performance and area for next-generation 5G and AI/ML SoC design SAN JOSE, Calif. -- May 18, 2020-- Cadence Design Systems, Inc. (Nasdaq: CDNS) ...