Semiconductor Engineering

Better ATPG To Minimize Chip Test Time And Cost

As chips get ever bigger and more complex, the electronic design automation (EDA) industry must innovate constantly to keep up. Engineers expect every new generation of silicon to be modeled, ...
Semiconductor Engineering

Can Your ATPG Do This? Cut Defects Escaping Detection With ML

Chipmakers worldwide consider Automatic Test Pattern Generation (ATPG) their go-to method for achieving high test coverage in production. ATPG generates test patterns designed to detect faults in the ...
Design-Reuse

BIST versus ATPG -- separating myths from reality

There is a rapidly growing interest in the use of structural techniques for testing random logic. In particular, much has been published on new techniques for on-chip compression of automatic test ...
Design-Reuse

SOC: Submicron Issues -> Heading off test problems posed by SoC

Ron Press, Technical Marketing Manager, ATPG Products, Janusz Rajski, Chief Scientist and Business Unit Manager, ATPG Product Group, Mentor Graphics Corp., Wilsonville, Ore. A system-on-chip is a ...