GitHub

jkhlim125/Systolic-Array-Accelerator

This project implements a 4×4 systolic array accelerator in Verilog and analyzes its execution behavior using a Python-based visualization pipeline. The focus is on building a cycle-accurate hardware ...
GitHub

SAURIA - Systolic Array tensor Unit for aRtificial Intelligence Acceleration

SAURIA is a Convolutional Neural Network (CNN) accelerator based on an output stationary (OS) systolic array with on-chip, on-the-fly convolution lowering, written entirely in SystemVerilog. The ...
IEEE

Novel FPGA based Systolic Array Design for Dynamic Workflows

Abstract: Convolutional neural network based object detection is an inevitable part of advanced driver assistance systems which has high accuracy and low latency requirements. Considering the high ...
IEEE

FAMS: A FrAmework of Memory-Centric Mapping for DNNs on Systolic Array Accelerators

Abstract: In recent years, deep neural networks (DNNs) have experienced rapid development. These DNNs demonstrate significant variations in architecture and scale, creating a substantial demand for ...